Franzon Investigates Scalability of Hardware Accelerators for Cortical Processors
Dr. Paul Franzon, distinguished professor of electrical and computer engineering, has been awarded $705,602 by the US Air Force (USAF) to research new architectures for implementing cognitive algorithms.
March 2, 2015 
NC State ECE
Dr. Paul Franzon
Artificial Intelligence is a fast growing field. There are numerous cognitively inspired machine learning algorithms that attempt to model aspects of the human brain, several of which have had significant commercial and/or research success.
However, the current implementation of these algorithms use hundreds of thousands of simple computing nodes that are highly interconnected. One of the problems with this implementation is inefficiency due to many potential nodes being inactive. Another problem is that because the nodes are highly connected, the algorithms map poorly on to current conventional computers which quickly become memory bound and interconnect bound.
Dr. Paul Franzon, distinguished professor of electrical and computer engineering, has been awarded $705,602 by the US Air Force (USAF) to research new architectures for implementing cognitive algorithms.
New distributed processor architectures must be designed to reflect the distributed nature of the algorithms. Two processor solutions will be investigated, a configurable programmable one and a more highly customized but still configurable one.
In addition, a small number of solutions to the interconnectivity problem will be investigated to support the required I/O and cross-system bandwidth needs with minimal overhead. These include a memory style interconnect solution, a token ring solution as well as a hierarchical network one, and optionally, the concept of a wafer scale interposer. 2.5D and 3D architectures will be investigated for physical implementation.
According to Dr. Franzon, the preliminary results are encouraging. “Investigation of a custom processor for HTM for digit recognition (e.g. for postal sorting) found a 300,000x improvement in performance per unit of power over a parallel processor solution. In a separate investigation with a full ASIC implementation, inference was sped up by 2100 times over a single processor solution. Some applications include action recognition in videos and robotic self mapping and navigation.”
The award will run from December 1st, 2014 to June 15th, 2016.