How students are tackling unstructured data indexing with POWER8
North Carolina State University is one of the participants in the Innov8 with POWER8 Challenge. Utilizing technology from IBM and OpenPOWER Foundation members including NVIDIA, Mellanox and Altera, I’m overseeing a team that is working on a custom Fiel …
January 13, 2015 By NC State ECE
North Carolina State University is one of the participants in the Innov8 with POWER8 Challenge. Utilizing technology from IBM and OpenPOWER Foundation members including NVIDIA, Mellanox and Altera, I’m overseeing a team that is working on a custom Field Programmable Gate Array (FPGA) accelerator for analytics software to quickly index unstructured data, a process that until this point has been extremely time-consuming. We’re just getting started and we’re excited to have early access to the cutting-edge POWER8 technology.
Business analytics tools, such as IBM BigInsights and Watson Content Analytics, require extensive document pre-processing before the data is ready to present answers to users. This step is often the most time-consuming and is a major impediment preventing the move from off-line to on-line analytics. With this in mind, our goal is to exploit the Coherent Accelerator Programming Interface (CAPI) of the POWER8 architecture to offload some of this preprocessing work to a custom FPGA-based accelerator.
At NC State, we have identified that indexing is a major overhead and have decided to tackle this issue first. Since indexing is built on the open-source Lucene package, our work will start by analyzing the performance of Lucene on POWER8 and isolate one or more computational kernels that can benefit from FPGA acceleration. From there, we plan to design an accelerator and adapt the software, using CAPI, to exploit coherent memory transfer between the processing cores and the accelerator hardware.
Because CAPI allows the FPGA accelerator to be attached directly to the memory bus, rather than to the I/O bus, reducing latency and simplifying the programming model, the accelerator becomes a peer to the processor, and it shares the same virtual address space. The shared memory eliminates the need for explicit DMA to transfer data to and from the accelerator. The “coherent” part of the interface means that the memory loads and stores are observed by the cache subsystem on the processor, and all relevant coherence actions are taken. This means there’s no need to flush the caches or to use non-cacheable data.
As I mentioned, we are in the beginning stages of this process and are excited to implement and test our design! I have three MS students working with me on this project: Thomas Paradis (on the left), Yifang Zhao (in the middle) and Aditya Shirole (on the right).
We have a POWER8 server, and we will be getting a loaner FPGA card when we’re ready to implement and test our design. (Ours is the second from the top.) The server is housed in the OSCAR lab (Open Source Collaboration and Research) at NC State, which is sponsored by IBM, along with other industry leaders like Red Hat. Special thanks to John Streck and Jay Hall for hosting the server and doing all of the setup.
We are grateful to IBM and the other OpenPOWER Foundation members – including NVIDIA, Altera and Mellanox – for creating and supporting this challenge, and we look forward to hearing about the other projects. We’ll report back with our progress. In the meantime, follow along and join the #innov8power8 conversation.
Source: Smarter Computing blog written by Dr. Gregory Byrd; posted with permission.
Dr. Gregory Byrd is Professor and Associate Department Head, Electrical and Computer Engineering at North Carolina State University. Dr. Byrd’s primary research is in the area of high-performance parallel systems and servers. He is interested in mechanisms which reduce communication overhead in parallel and distributed systems. Other areas of interest include computer architecture, network processing, service-oriented computing, and network security. Connect with him via the department on Twitter and Facebook.
Associate Department Head