Towards High-Performance Simulation of Hardware Designs
Currently, the focus is to develop a library, known as NC State University (NCSU) Library, that facilitates evaluation of hardware designs at various levels of abstraction and provides support for various hardware description languages, such as Verilog and SystemC.
This project focuses on developing a library, NC State Library, to evaluate hardware designs at different levels of abstraction and support multiple hardware description languages, such as Verilog and SystemC. Through this library and available parallel discrete event-based simulation frameworks like SST simulator, researchers can simulating hardware designs written in low-level hardware languages. Ultimately, this project will enable high-performance simulation of hardware designs.
Sponsor
National Technology and Engineering Solutions of Sandia, LLC. (Sandia National Laboratories)
The grant—running from October 1, 2020 to September 30, 2022—is for a total of $175,000.
Principle Investigators
Amro Awad
More Details
This work aims to explore new techniques for high-performance simulation of hardware designs. The ultimate outcome of the project is to enable researchers of simulating hardware designs written in low-level hardware languages using available parallel discrete event-based simulation frameworks, such as SST simulator.